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fn9182 rev 2.00 page 1 of 15 april 4, 2006 fn9182 rev 2.00 april 4, 2006 ISL6753 zvs full-bridge pwm controller datasheet the ISL6753 is a high-per formance, low -pin-count alternative, zero-voltage switching (zvs) full-bridge pwm controller. like the isl6551, i t achieves zvs operation by driving the upper bri dge fets at a fixed 50% duty cycle while the lower bridge fets are t railing-edge modulated with adjustable resonant switching delays. compared to the more familiar phase-shift ed control method, th is algorithm offers equivalent efficiency and impr oved overcurrent and light- load performance with less complexity in a lower pin count package. this advanced bicmos desig n features low operating current, adjustable oscilla tor frequency up to 2mhz, adjustable soft-start, internal over temperatur e protection, precision deadtime and reson ant delay control, and short propagation delays. additionally, multi-pulse suppression ensures alternating output pul ses at low duty cycles where pulse skipping may occur. features ? adjustable resonant delay for zvs operation ? voltage- or current-mode operation ? 3% current limit threshold ? 175 ? a startup current ? supply uvlo ? adjustable deadtime control ? adjustable soft-start ? adjustable oscillator frequency up to 2mhz ? tight tolerance error amplif ier reference over line, load, and temperature ? 5mhz gbwp error amplifier ? adjustable cycle-by-cycle peak current limit ? fast current sense to output delay ? 70ns leading edge blanking ? multi-pulse suppression ? buffered oscillator sawtooth output ? internal over temp erature protection ? pb-free plus anneal available and elv, weee, rohs compliant applications ? zvs full-bridge converters ? telecom and datacom power ? wireless base station power ? file server power ? industrial power systems ordering information part number part marking temp. range (c) package pkg. dwg. # ISL6753aaza (see note) ISL6753aaz -40 to 105 16 ld qsop (pb-free) m16.15a add -t suffix to part number for tape and reel packaging note: intersil pb-free plus anneal products employ special pb-fr ee material sets; molding compounds/ die attach materials and 100% matte tin plate termination finish , which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. pinout ISL6753 (qsop) top view rtd ss ct outur outul ctbuf outlr resdel ramp outll fb vdd verr vref cs gnd 1 2 4 3 5 6 7 89 10 11 12 13 14 15 16
fn9182 rev 2.00 page 2 of 15 april 4, 2006 ISL6753 functional block diagram outll outlr outul outur vdd pwm steering logic resdel uvlo over- temperature protection vref oscillator ct rtd vdd gnd vref ramp + - + - 0.6v 0.33 80mv vref softstart control vref 50% pwm verr fb 1 ma ss ctbuf cs pwm comparator + - 1.00v over current comparator 70 ns leading edge blanking
fn9182 rev 2.00 page 3 of 15 april 4, 2006 ISL6753 typical application - high voltage input zvs full-b ridge converter p1 vin+ p2 vin- p4 return t2 p8205 r7a, b 18.7 0805 c8 1.0nf c9 0.47uf c18 1uf 100v 1210 c5 0.1uf r1 4.7k 5% 2512 r3 4.7k 5% 2512 r2 4.7k 5% 2512 q11 mjd50 300 - 400 vdc u1 ISL6753 l1 pb2020.103 t1 r5 100k 1206 vr1 bzx84-c12 r8 45.3k p3 + vout (48v@10a) c19 1uf 100v 1210 c20 470uf 63v c21 470uf 63v c1-c4 33uf 450v q2 fqb6n50 q3 fqb6n50 r11 3.65k r10 10.0k r18 10 5% 2512 r19 10 2512 c10 0.1uf c6 180pf 5% cog c13 0.1uf c15 220pf c16 100pf 250v cog t3 p0544 cr4 ss12 cr3 ss12 cr5 csd10060g cr6 csd10060g + + + q8 zxtdb2m832 q7 zxtdb2m832 r21 3.74k 1206 r23 1.10k c14 4.7nf c17 100pf 250v cog u3 r25 37.4k 0805 r20 499 r24 100k q9 zxtdb2m832 q10 zxtdb2m832 u2 ps2701-1p cr1 bav70 q1 fqb6n50 q4 fqb6n50 r4 4.7k 5% 2512 r6 5.11k r9 499 c7 47pf rtd ss ct outur outul ctbuf outlr resdel ramp outll fb1 vdd verr vref cs gnd r12 20.0k q6 bss138lt1 q5 bss138lt1 np ns ns r13 10.0k r14 4.99 0805 r15 4.99 0805 r16 10.0k r17 10.0 r26 10.0k 0805 c11 0.1uf c12 1.0uf r28 10.0k 2512 vr2 bzx84-c6v8 + + + cr2 bat54c 1 2 3 1 2 3 3 1 3 2 1 7 8 31 6 3 4 5 8 1 3 1 4 2 5,6 7,8 3 1 4 2 5,6 7,8 3 1 4 2 5,6 7,8 3 1 4 2 5,6 7,8 3 2 1 4 2 3 1 1 3 2 3 1 2 3 1 2 2 1,c 1,c r27 10.0k 0805 r22 3.74k 1206 c22 4700pf 250vac safety c23 4700pf 250vac safety r29 20.0k r30 20.0k 2, 3 6, 7 13, 14 11, 12 9, 10 15, 16 cr7 bat54 31 2 bias
ISL6753 fn9182 rev 2.00 page 4 of 15 april 4, 2006 absolute maximum ratings thermal information supply voltage, vdd . . . . . . . . . . . . . . . . . . . gnd - 0.3v to +20.0v outxxx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to vdd signal pins . . . . . . . . . . . . . . . . . . . . . . . gnd - 0 .3v to v ref + 0.3v vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd - 0.3v to 6.0v peak gate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1a esd classification human body model (per mil-std-883 method 3015.7) . . .3000v charged device model (per eos/esd ds5.3, 4/14/93) . . .1000v operating conditions temperature range ISL6753aaxx . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to 105c supply voltage range (typical). . . . . . . . . . . . . . . . . . . . 9-16 vdc thermal resistance (typical) ? ja (c/w) 16 lead qsop (note 1). . . . . . . . . . . . . . . . . . . . . . 95 maximum junction temperature . . . . . . . . . . . . . . . . -55 c to 150c maximum storage temperature range . . . . . . . . . . . -65c to 150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300c (qsop- lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. notes: 1. ? ja is measured with the component mounted on a high effective the rmal conductivity test board in free air. see tech brief tb379 for details. 2. all voltages are with respect to gnd. electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram and typical application schematic. 9v < vdd < 20v, rtd = 10.0k ? , ct = 470pf, t a = -40 c to 105 c (note 3), typical values are at t a = 25 c parameter test conditions min typ max units supply voltage supply voltage --20- start-up current, idd vdd = 5.0v - 175 400 ? a operating current, idd r load , c out = 0 - 11.0 15.5 ma uvlo start threshold 8.00 8.75 9.00 v uvlo stop threshold 6.50 7.00 7.50 v hysteresis -1.75- v reference voltage overall accuracy i vref = 0 - -10ma 4.850 5.000 5.150 v long term stability t a = 125c, 1000 hours (note 4) - 3 - mv operational current (source) -10 - - ma operational current (sink) 5 - - ma current limit vref = 4.85v -15 - -100 ma current sense current limit threshold verr = vref 0.97 1.00 1.03 v cs to out delay excl. leb (note 4) - 35 50 ns leading edge blanking (leb) duration (note 4) 50 70 100 ns cs to out delay + leb t a = 25c - - 130 ns cs sink current device impedance v cs = 1.1v - - 20 ? input bias current v cs = 0.3v -1.0 - 1.0 ? a ramp ramp sink current device impedance v ramp = 1.1v - - 20 ? ramp to pwm comparator offset t a = 25c 658095mv
ISL6753 fn9182 rev 2.00 page 5 of 15 april 4, 2006 bias current v ramp = 0.3v -5.0 - -2.0 ? a clamp voltage (note 4) 6.5 - 8.0 v pulse width modulator minimum duty cycle verr < 0.6v - - 0 % maximum duty cycle (per half-cycle) verr = 4.20v, v ramp = 0v, v cs = 0v (note 5) - 94 - % rtd = 2.00k ? , ct = 220pf - 97 - % rtd = 2.00k ? , ct = 470pf - 99 - % zero duty cycle verr voltage 0.85 - 1.20 v verr to pwm comparator input offset t a = 25c 0.7 0.8 0.9 v verr to pwm comparator input gain 0.31 0.33 0.35 v/v common mode (cm) input range (note 4) 0 - v ss v error amplifier input common mode (cm) range (note 4) 0 - vref v gbwp (note 4) 5 - - mhz verr vol i load = 2ma - - 0.4 v verr voh i load = 0ma 4.20 - - v verr pull-up current source verr = 2.5v 0.8 1.0 1.3 ma ea reference t a = 25c 0.594 0.600 0.606 v ea reference + ea input offset voltage 0.590 0.600 0.612 v oscillator frequency accuracy, overall (note 4) 165 183 201 khz -10 - +10 % frequency variation with vdd t a = 25c, (f 20v - - f 10v )/f 10v -0.31.7% temperature stability vdd = 10v, |f -40c - f 0c |/f 0c -4.5- % |f 0c - f 105c |/f 25c (note 4) -1.5- % charge current t a = 25c -193 -200 -207 ? a discharge current gain 19 20 23 ? a/ ? a ct valley voltage static threshold 0.75 0.80 0.88 v ct peak voltage static threshold 2.75 2.80 2.88 v ct pk-pk voltage static value 1.92 2.00 2.05 v rtd voltage 1.97 2.00 2.03 v resdel voltage range 0 - 2 v ctbuf gain (v ctbufp-p /v ctp-p )v ct = 0.8v, 2.6v 1.95 2.0 2.05 v/v ctbuf offset from gnd v ct = 0.8v 0.34 0.40 0.44 v ctbuf voh ? v(i load = 0ma, i load = -2ma), v ct = 2.6v - - 0.10 v electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram and typical application schematic. 9v < vdd < 20v, rtd = 10.0k ? , ct = 470pf, t a = -40 c to 105 c (note 3), typical values are at t a = 25 c (continued) parameter test conditions min typ max units
ISL6753 fn9182 rev 2.00 page 6 of 15 april 4, 2006 ctbuf vol ? v(i load = 2ma, i load = 0ma), v ct = 0.8v - - 0.10 v soft-start charging current ss = 3v -60 -70 -80 ? a ss clamp voltage 4.410 4.500 4.590 v ss discharge current ss = 2v 10 - - ma reset threshold voltage t a = 25c 0.23 0.27 0.33 v outputs high level output voltage (voh) i out = -10ma, vdd - voh - 0.5 1.0 v low level output voltage (vol) i out = 10ma, vol - gnd - 0.5 1.0 v rise time c out = 220pf, vdd = 15v(note 4) - 110 200 ns fall time c out = 220pf, vdd = 15v(note 4) - 90 150 ns uvlo output voltage clamp vdd = 7v, i load = 1ma (note 6) - - 1.25 v thermal protection thermal shutdown (note 4) 130 140 150 c thermal shutdown clear (note 4) 115 125 135 c hysteresis, internal pro tection (note 4) - 15 - c notes: 3. specifications at -40c and 105c are guaranteed by 25c test with margin limits. 4. guaranteed by design, not 100% tested in production. 5. this is the maximum duty cycle achievable using the specified values of rtd and ct. larger or smaller maximum duty cycles ma y be obtained using other values for these components. see equations 1 - 5. 6. adjust vdd below the uvlo stop threshold prior to setting at 7v. electrical specifications recommended operating conditions unless otherwise noted. refer to block diagram and typical application schematic. 9v < vdd < 20v, rtd = 10.0k ? , ct = 470pf, t a = -40 c to 105 c (note 3), typical values are at t a = 25 c (continued) parameter test conditions min typ max units
ISL6753 fn9182 rev 2.00 page 7 of 15 april 4, 2006 pin descriptions vdd - vdd is the power connection for the ic. to optimize noise immunity, bypass v dd to gnd with a ceramic capacitor as close to the vdd and gn d pins as possible. supply voltage under-voltage lock-out (uvlo) start and stop thresholds track each other resulting in r elatively constant hysteresis. gnd - signal and power ground connections for this device. due to high peak currents a nd high frequency operation, a low impedance layout is nec essary. ground planes and short traces are highly recommended. vref - the 5.00v reference voltage output having 3% tolerance over line, load and operating temperature. bypass to gnd with a 0.1 ? f to 2.2 ? f low esr capacitor. ct - the oscillator timing capacitor is connected between this pin and gnd. it is char ged through an internal 200 ? a current source and discharged wit h a user adjustable current source controlled by rtd. rtd - this is the oscillator ti ming capacitor discharge current control pin. the curr ent flowing in a resistor connected between this pi n and gnd determines the magnitude of the current t hat discharges ct. the ct discharge current is nominally 20x the resistor current. the pwm deadtime is determined by the timing capacitor discharge duration. the voltage at rtd is nominally 2.00v. cs - this is the input to the overcurrent comparator. the overcurrent comparator thresho ld is set at 1.00v nominal. the cs pin is shorted to gnd at the termination of either pwm output. depending on the current sens ing source impedance, a series input resistor may be required due to the delay between the internal clock a nd the external power switch. this delay may result in cs bei ng discharged prior to the power switching devi ce being turned off. ramp - this is the input for the sawtooth waveform for the pwm comparator. the ramp pin is shorted to gnd at the termination of the pwm signa l. a sawtooth voltage typical performance curves figure 1. reference voltage vs te mperature figure 2. ct discharge current gain vs rtd current figure 3. deadtime (dt) vs capacitance figure 4. capacitance vs fr equency 40 25 105 203550658095110 0.98 0.99 1 1.01 1.02 temperature (c) normalized vref 0 200 400 600 800 1000 18 19 20 21 22 23 24 25 rtd current (ua) ct discharge current gain 0 102030405060708090100 10 100 1 ? 10 3 1 ? 10 4 rtd (kohms) deadtime - td (ns) ct = 1000pf 680pf 470pf 330pf 220pf 100pf 0.1 1 10 10 100 1 ? 10 3 ct (nf) frequency (khz) rtd= 10k ? 50k ? 100k ?
ISL6753 fn9182 rev 2.00 page 8 of 15 april 4, 2006 waveform is required at this inp ut. for current -mode control this pin is connected to cs and the current loop feedback signal is applied to both inpu ts. for voltage-mode control, the oscillator sawtooth wavef orm may be buffered and used to generate an appropriate si gnal, ramp may be connected to the input voltage through a rc network for voltage feed forward control, or ramp m ay be connected to vref through a rc network to produce the desired sawtooth waveform. outul and outur - these outputs c ontrol the upper bridge fets and oper ate at a fixed 5 0% duty cycle in alternate sequence. outul controls the upper left fet and outur controls the upper ri ght fet. the left and right designation may be switched as long as they are switched in conjunction with the lower fet outputs, outll and outlr. resdel - sets the resonant delay period between the toggle of the upper fets and t he turn on of e ither of the lower fets. the voltage app lied to resdel determines when the upper fets switch relat ive to a lower fet turning on. varying the control voltage from 0 to 2.00v increases the resonant delay duration from 0 to 100% of the deadtime. the control voltage divided by 2 r epresents the percent of the deadtime equal to the resonant delay. in practice the maximum resonant delay must be set lower than 2.00v to ensure that the lower fets, at maximum duty cycle, are off prior to the switching of the upper fets. outll and outlr - these outputs cont rol the lower bridge fets, are pulse width modulated, and operate in alternate sequence. outll controls the lower left fet and outlr controls the lower ri ght fet. the left and right designation may be switched as long as they are switched in conjunction with the upper fet outputs, outul and outur. verr - the control voltage input to the inverting input of the pwm comparator. the output of an exter nal error amplifier (ea) is applied to this input for closed loop regulation. verr has a nominal 1ma pull-up current source. fb - fb is the inverting input to the error amplifier (ea). ss - connect the soft-start timing capacitor between this pin and gnd to control the duration of soft-start. the value of the capacitor determines the rate of increase of the duty cycle during start-up. ss may also be used to inhibit the outputs by grounding through a small transistor in an open collector/drain configuration. ctbuf - ctbuf is the buffered output of the sawtooth oscillator waveform present on ct and is capable of sourcing 2ma. it is offset fro m ground by 0.40v and has a nominal valley-to-peak gain of 2. it may be used for slope compensation. functional description features the ISL6753 pwm is an excell ent choice for low cost zvs full-bridge applications employing conventional output rectification. if synchronous rec tification is required, please consider the isl6752 or isl6551 products. with the ISL6753s many protect ion and control features, a highly flexible design with mi nimal external components is possible. among its many feat ures are support for both current- and voltage-mode c ontrol, a very accurate overcurrent limit threshold, t hermal protection, a buffered sawtooth oscillator output suit able for slope compensation, voltage controlled resonant delay, and adjustable frequency with precise deadtime control. oscillator the ISL6753 has an oscill ator with a programmable frequency range to 2mhz, and can be progra mmed with an external resistor and capacitor. the switching period is the sum of the timing capacitor charge and discharge durati ons. the charge duration is determined by ct and a fixed 200 ? a internal current source. the discharge duration is d etermined by rtd and ct. where t c and t d are the charge and discharge times, respectively, t sw is the oscillator period, and f sw is the oscillator frequency. one outpu t switching cycle requires two oscillator cycles. the actual tim es will be slightly longer tha n calculated due to interna l propagation delays of approximately 10ns/transition. this delay adds directly to the switching duration, but also ca uses overshoot of the timing capacitor peak and valley volt age thresholds, effectively increasing the peak-to-peak volta ge on the timing capacitor. additionally, if very small disc harge currents are used, there will be increased error due to the input impedance at the ct pin. the maximum duty cycle, d, and percent deadtime, dt, can be calculated from: t c 11.5 10 ? 3 ct ? ? s (eq. 1) t d 0.06 rtd ct ?? ?? 50 10 9 C ? + ? s (eq. 2) t sw t c t d + 1 f sw ------------ == s (eq. 3) d t c t sw ------------ = (eq. 4) dt 1 d C = (eq. 5)
ISL6753 fn9182 rev 2.00 page 9 of 15 april 4, 2006 soft-start operation the ISL6753 features a soft-star t using an external capacitor i n conjunction with an internal current source. soft-start reduces component stresses and surge c urrents during start-up. upon start-up, the sof t-start circuitry limits the error voltag e input (verr) to a value equal to the soft-start voltage. the output pulse width increases a s the soft-start capacitor voltage increases. this has the effect of increasing the duty cycle from zero to the regulation pulse width during the soft- start period. when the soft-sta rt voltage exceeds the error voltage, soft-start is complete d. soft-start occurs during start-up and after recovery from a fault condition. the soft- start charging period may be calculated as follows: where t is the charging period in ms and c is the value of the soft-start capacitor in ? f. the soft-start voltage is clamped to 4.50v with a tolerance of 2%. it is suitable for use as a soft-started reference provided the current draw is kept well below the 70 ? a charging current. the outputs may be inhibited by using the ss pin as a disable input. pulling ss below 0 .25v forces all outputs low. an open collector/drain configuration may be used to couple the disable signal into the ss pin. gate drive the ISL6753 outputs are capable of sourcing and sinking 10ma (at rated voh, vol) and are intended to be used in conjunction with integrated fet drivers or discrete bipolar totem pole drivers. the typical on resistance of the outputs is 50 ? . overcurrent operation the cycle-by-cycle peak current l imit results in pulse-by-pulse duty cycle reduction when t he current feedback signal exceeds 1.0v. when the peak current exceeds the threshold, the active output pulse is immedi ately terminated. this results in a decrease in output voltage as the load current increases beyond the current limit threshold. the ISL6753 operates continuously in an ov ercurrent condition without shutdown. if voltage-mode control is used in a bridge topology, it should be noted that peak current limit r esults in inherently unstable operation. the dc blocking capacitors used in voltage-mode bridge topologies become unbalanced, as does the flux in the transformer core. a latching overcurrent shutdown method using external components is recommended. the propagation delay from cs exceeding the current limit threshold to the termination of t he output pulse is increased by the leading edge blanking (le b) interval. the effective delay is the sum of t he two delays and is nominally 105ns. voltage feed forward operation voltage feed forward is a tech nique used to regulate the output voltage for changes i n input volta ge without the intervention of the control loop. voltage feed forward is often implemented in voltage-mode control loops, but is redundant and unnecessary in peak current-mode control loops. voltage feed forward operates by modulating the sawtooth ramp in direct proportion to the input voltage. figure 5 demonstrates the concept. input voltage feed forward may be implemented using the ramp input. an rc network co nnected between the input voltage and ground, as shown in figure 7, generates a voltage ramp whose charging ra te varies with the amplitude of the source voltage. at the te rmination of the active output pulse ramp is discharged to gr ound so that a repetitive sawtooth waveform is creat ed. the ramp waveform is compared to the verr voltage to determine duty cycle. the selection of the rc compo nents depends upon the desired input voltage operating rang e and the frequency of the oscillator. in typical applic ations the rc components are selected so that the ramp amplitude reaches 1.0v at minimum input voltage within th e duration of one half-cycle. t 64.3 c ? = ms (eq. 6) figure 5. voltage feed forward behavior vin error voltage ramp ct outll lr figure 6. voltage feed forward control vin r3 c7 gnd 1 2 4 3 5 6 7 89 10 11 12 13 14 15 16 ramp ISL6753
ISL6753 fn9182 rev 2.00 page 10 of 15 april 4, 2006 the charging time of the ramp capacitor is for optimum performance, the maximum value of the capacitor should be limited to 10nf. the maximum dc current through the resist or should be lim ited to 2ma maximum. for examp le, if the oscilla tor frequency is 400khz, the minimum input vo ltage is 300v, and a 4.7nf ramp capacitor is selected, t he value of the resistor can be determined by rearranging equation 7. where t is equal to the oscillator period minus the deadtime. if the deadtime is short relative to the oscillator period, it can be ignored for this calculation. if feed forward operation is not desired, the rc network may be connected to vre f rather than the input voltage. alternatively, a resistor divi der from ctbuf may be used as the sawtooth signal. regardless, a sawtooth waveform must be generated on ramp as it i s required for proper pwm operation. slope compensation peak current-mode control req uires slope compensation to improve noise immunity, particul arly at lighter loads, and to prevent current loop instability , particularly for duty cycles greater than 50%. slo pe compensation may be accomplished by summing an external ramp with the current feedback signal or by subtracting the external ramp from the voltage feedback error signal. a dding the external ramp to the current feedback signal is the more popular method. from the small signal curr ent-mode model [1 ] it can be shown that the naturally-sam pled modulator gain, fm, without slope compensation, is where sn is the slope of the sa wtooth signal and tsw is the duration of the half-cycle. wh en an external ramp is added, the modulator gain becomes where se is slope of the external ramp and the criteria for determining t he correct amount of external ramp can be determined by app ropriately setting the damping factor of the doubl e-pole located at half the oscillator frequency. the d ouble-pole will be critically damped if the q-fac tor is set to 1, a nd over-damped for q > 1, and under-damped fo r q < 1. an under-damped condition can result in current loop instability. where d is the percent of on t ime during a half cycle. setting q = 1 and solving for se yields: since s n and s e are the on time slopes of the current ramp and the external ramp, respect ively, they can be multiplied by ton to obtain the voltage ch ange that occurs during ton. where vn is the change in the current feedback signal during the on time and ve is the vol tage that must be added by the external ramp. vn can be solved for in terms of input voltage, current transducer components, and output inductance yielding: where r cs is the current sense burden resistor, n ct is the current transformer turns ratio, l o is the output inductance, v o is the output voltage, and ns and np are the secondary and primary turns, respectively. the inductor current, when ref lected through the isolation transformer and the current sense transformer to obtain the current feedback signal at t he sense resistor yields: where v cs is the voltage across t he current sense resistor and i o is the output current at current limit. since the peak curre nt limit threshold i s 1.00v, the total current feedback signal plus the external ramp voltage must sum to this value. substituting equations 15 and 16 into equation 17 and solving for r cs yields tr3c71 v ramp peak ?? v in min ?? --------------------------------------- - C ?? ?? ?? ln ?? C = s (eq. 7) r3 t C c7 1 v ramp peak ?? v in min ? ?? --------------------------------------- - C ?? ?? ?? ln ? --------------------------------------------------------------- ---------- 2.5 C 10 6 C ? 4.7 10 9 C 1 1 300 --------- - C ?? ?? ln ?? ------------------------------------------------------------ == 159 = k ? (eq. 8) fm 1 sntsw ------------------- - = (eq. 9) fm 1 sn se + ?? tsw -------------------------------------- - 1 m c sntsw ---------------------------- == (eq. 10) m c 1 se sn ------- + = (eq. 11) q 1 ? m c 1d C ?? 0.5 C ?? ------------------------------------------------- = (eq. 12) s e s n 1 ? -- - 0.5 + ?? ?? 1 1d C ------------- 1 C ?? ?? = (eq. 13) v e v n 1 ? -- - 0.5 + ?? ?? 1 1d C ------------- 1 C ?? ?? = (eq. 14) v e t sw v ? o r cs ? n ct l o ? ----------------------------------------- - n s n p ------- - ? 1 ? -- - d0.5 C + ?? ?? = v (eq. 15) v cs n s r cs ? n p n ct ? ------------------------ i o dt ? sw 2l o --------------------- v in n s n p ------- - ? v o C ?? ?? ?? + ?? ?? ?? = v (eq. 16) v e v cs + 1 = (eq. 17) r cs n p n ct ? n s ------------------------ 1 i o v o l o ------- - t sw 1 ? -- - d 2 --- - + ?? ?? + ------------------------------------------------------ ? = ? (eq. 18)
ISL6753 fn9182 rev 2.00 page 11 of 15 april 4, 2006 for simplicity, idealized components have been used for this discussion, but the effect of magnetizing inductance must be considered when determining t he amount of external ramp to add. magnetizing inductance provides a degree of slope compensation to the current feedback signal and reduces the amount of external ramp required. the magnetizing inductance adds primary cu rrent in excess of what is reflected from the inductor current in the secondary. where v in is the input voltage that corresponds to the duty cycle d and lm is the primary magnetizing inductance. the effect of the magnetizing cu rrent at the current sense resistor, r cs , is if ? v cs is greater than or equal t o ve, then no additional slope compensation is needed and r cs becomes if ? v cs is less than ve, then equatio n 18 is still valid for the value of r cs , but the amount of slope compensation added by the external ramp must be reduced by ? v cs . adding slope compensation is a ccomplished in the ISL6753 using the ctbuf signal. c tbuf is an amplified representation of the sawtooth si gnal that appears on the ct pin. it is offset from ground b y 0.4v and is 2x the peak-to- peak amplitude of ct (0.4 - 4.4v). a typical application sums this signal with the current sense feedback and applies the result to the cs pin a s shown in figure 7. assuming the designer has select ed values for the rc filter placed on the cs pin , the value of r9 required to add the appropriate external ramp c an be found by superposition. rearranging to solve for r9 yields the value of r cs determined in equation 18 must be rescaled so that the current s ense signal presented at the cs pin is that predicted by eq uation 16. the divider created by r6 and r9 makes this necessary. example: v in = 280v v o = 12v l o = 2.0 ? h np/ns = 20 lm = 2mh i o = 55a oscillator frequency, fsw = 400khz duty cycle, d = 85.7% n ct = 50 r6 = 499 ? solve for the current sense resistor, r cs , using equation 18. r cs = 15.1 ? . determine the amount of voltage , ve, that must be added to the current feedback signal using equation 15. ve = 153mv next, determine the effect o f the magnetizing current from equation 20. ? v cs = 91mv using equation 23, solve for t he summing resistor, r9, from ctbuf to cs. r9 = 30.1k ? determine the new value of r cs , r cs , using equation 24. r cs = 15.4 ? the above discussion determi nes the minimum external ramp that is required. additional slope compensation may be considered for design margin. i p ? v in dt sw ? l m ------------------------------- = a (eq. 19) ? v cs ? i p r cs ? n ct ------------------------- - = v (eq. 20) r cs n ct n s n p ------- - i o dt sw 2l o ----------------- v in n s n p ------- - ? v o C ?? ?? ?? ? + ?? ?? ?? ? v in dt sw ? l m ------------------------------- + --------------------------------------------------------------- --------------------------------------------------------------- ------- - = (eq. 21) figure 7. adding slope compensation r6 c4 r9 ctbuf cs 1 2 4 3 5 6 7 8 r cs ISL6753 v e ? v cs C dv ctbuf 0.4 C ?? 0.4 + ?? r6 ? r6 r9 + --------------------------------------------------------------- ---------------- = v (eq. 22) r9 dv ctbuf 0.4 C ?? v e ? v cs 0.4 ++ C ?? r6 ? v e ? v cs C --------------------------------------------------------------- --------------------------------------------------- - = ? (eq. 23) r ? cs r6 r9 + r9 ---------------------- r cs ? = (eq. 24)
ISL6753 fn9182 rev 2.00 page 12 of 15 april 4, 2006 if the application requires d eadtime less than about 500ns, the ctbuf signal may not pe rform adequately for slope compensation. ctbuf lags the ct sawtooth waveform by 300-400ns. this behavior results in a non-zero value of ctbuf when the next half-cycle begi ns when the deadtime is short. under these situations, slope compensation may be added by externally buffering the ct signal as shown below. using ct to provide slope co mpensation instead of ctbuf requires the same calculatio ns, except that equations 21 and 22 require mod ification. equation 21 becomes: and equation 22 becomes: the buffer transistor used to c reate the external ramp from ct should have a sufficiently high gain so as to minimize the required base current. whateve r base current is required reduces the charging current into ct and will reduce the oscillator frequency. zvs full-bridge operation the ISL6753 is a full-bridge ze ro-voltage switching (zvs) pwm controller that behaves m uch like a traditional hard- switched topology controller. ra ther than drive the diagonal bridge switches simultaneously , the upper switches (outul, outur) are driven at a fixed 50% duty cycle and the lower switches (outll, outlr) are pulse width modulated on the trailing edge. to understand how the zvs method operates one must include the parasitic elements of the circuit and examine a full switching cycle. in figure 10, the power semic onductor switch es have been replaced by ideal switch eleme nts with parallel diodes and capacitance, the output re ctifiers are ideal, and the transformer leakage inductan ce has been included as a discrete element. the parasitic capacitance has been lumped together as swit ch capacitance, but represents all parasitic capacitance in the circuit including winding capacitance. each switch is des ignated by its position, upper left (ul), upper right (ur), l ower left (ll), and lower right (lr). the beginning of the cycle, shown in figure 11, is arbitrarily set as having swit ches ul and lr on and ur and ll off. the direction of the p rimary and secondary currents are indicated by i p and i s , respectively. figure 8. adding slope compensation using ct r6 c4 r9 r cs ct ct cs 1 2 4 3 5 6 7 89 10 11 12 13 14 15 16 ISL6753 vref v e ? v cs C 2d r6 ? r6 r9 + ---------------------- = v (eq. 25) r9 2d v e ? v cs + C ?? r6 ? v e ? v cs C ------------------------------------------------------------ - = ? (eq. 26) figure 9. bridge drive signal timing ct deadtime outll outlr outur outul resdel window resonant delay pwm pwm pwm pwm figure 10. idealized full-bridge vin+ vin- ul ll ur lr vout+ rtn l l d2 d1
ISL6753 fn9182 rev 2.00 page 13 of 15 april 4, 2006 the ul - lr power transfer period terminates when switch lr turns off as determined by the pwm. the current flowing in the primary cannot be interr upted instantaneously, so it must find an alternate path . the current flows into the parasitic switch capacitance of lr and ur which charges the node to vin and then forwar d biases the body diode of upper switch ur. the primary leakage inductance, l l , maintains the current which now circulates around the path of switch ul, the transformer primary, and switch ur. when switch lr opens, the output inductor current fr ee-wheels through both output diodes, d1 and d2. during the switch transition, the output inductor current assists the leakage inductance in charging the upper and lower bridge fet capacitance. the current flow f rom the previous p ower transfer cycle tends to be maintained during the free-wheeling period because the transformer primary winding is essentially shorted. diode d1 may conduc t very little or none of the free-wheeling current, depending on circuit parasitics. this behavior is quite different t han occurs in a conventional hard-switched full-bridge topol ogy where the free-wheeling current splits nearly evenly be tween the output diodes, and flows not at all in the primary. this condition persists thro ugh the remainder of the half- cycle. during the period when ct discharges, also referred to as the deadtime, the upper switches toggle. switch ul turns off and switch ur turns on. the a ctual timing of the upper switch toggle is dependent on resdel which sets the resonant delay. the voltage applied to resdel determines how far in advance the toggle occurs prior to a lower switch turning on. the zvs transitio n occurs after the upper switches toggle and be fore the diagonal lower switch turns on. the required resonant delay is 1/4 of the period of the lc resonant frequency of the c ircuit formed by the leakage inductance and the parasitic capacitance. the resonant transition may be estima ted from equation 27. where ? is the resonant transition time, l l is the leakage inductance, c p is the parasitic capa citance, and r is the equivalent resistanc e in series with l l and c p . the resonant delay is always less than or equal to the deadtime and may be calcul ated using the following equation. where ? resdel is the desired resonant delay, v resdel is a voltage between 0 and 2v applied to the resdel pin, and dt is the deadtime (see equations 1 - 5). when the upper switches toggle , the primary current that was flowing through ul mus t find an alternate path. it charges/discharges the parasiti c capacitance of switches ul and ll until the body diode o f ll is forward biased. if resdel is set properly, switch ll will be tur ned on at this time.the output inductor does no t assist this transition. it is purely a resonant transition driven by the leakage inductance. figure 11. ul - lr power transfer cycle vin+ vin- ul ll ur lr vout+ rtn i p i s l l d2 d1 figure 12. ul - ur fr ee-wheeling period vin+ vin- ul ll ur lr vout+ rtn i p i s l l d2 d1 ? ? 2 -- - 1 1 l l c p -------------- - r 2 4l l 2 --------- - C ----------------------------------- = (eq. 27) ? resdel v resdel 2 -------------------- dt ? = s (eq. 28) vin+ vin- ul ll ur lr vout+ rtn l l d2 d1 i s i p figure 13. upper switch toggle and resonant transition
ISL6753 fn9182 rev 2.00 page 14 of 15 april 4, 2006 the second power transfer per iod commences when switch ll closes. with switches ur and ll on, the primary and secondary currents flow as indicated below. the ur - ll power transfer pe riod terminates when switch ll turns off as determined by the pwm. the current flowing in the primary must find an alt ernate path. the current flows into the parasitic switch capacitance which charges the node to vin and then forward bia ses the body diode of upper switch ul. as before , the output inductor c urrent assists in this transition. the primary leakage inductance, l l , maintains the current, which now circulates around the path of switch ur, the transformer primary, and switch ul. when switch ll opens, the output i nductor current free-wheels predominantly through diode d1. diode d2 may actually conduct very little or none of the free-wheeling current, depending on circuit parasitics. this condition persists through the remainder of the half-cycle. when the upper switches toggle, the primary current that was flowing through ur must f ind an alternate path. it charges/discharges the parasitic capacitance of switches ur and lr until the body diode o f lr is forward biased. if resdel is set proper ly, switch lr will be turned on at this time. the first power trans fer period commence s when switch lr closes and the cycle repeats. t he zvs transition requires that the leakage indu ctance has sufficien t energy stored to fully charge the parasitic cap acitances. since the energy stored is proportional to the square of the current (1/2 l l i p 2 ), the zvs resonant transition is load dependent. if the leakage inductance is not able to store sufficient energy for zvs, a discrete inductor may be added in series with the transformer primary. fault conditions a fault condition occurs if v ref or vdd fall below their undervoltage lockout (uvlo) th resholds or if the thermal protection is triggered. when a fault is detec ted, the soft- start capacitor is quickly di scharged, and th e outputs are disabled low. when the fault condition clears and the soft- start voltage is belo w the reset threshold, a soft-start cycle begins. an overcurrent condition is not considered a fault and does not result in a shutdown. thermal protection internal die over temperature protection is provided. an integrated temperatur e sensor protects the device should the junction temperature exceed 140c. there is approximately 15c of hysteresis. ground plane requirements careful layout is essential for satisfactory operation of the device. a good ground plan e must be employed. vdd and vref should be bypassed di rectly to gnd with good high frequency capacitance. references [1] ridley, r., a new continuous-time model for current mode control, ieee tr ansactions on power electronics, vol. 6, n o. 2, april 1991. vin+ vin- ul ll ur lr vout+ rtn l l d2 d1 figure 14. ur - ll power transfer figure 15. ur - ul fr ee-wheeling period vin+ vin- ul ll ur lr vout+ rtn i p i s l l d2 d1 vin+ vin- ul ll ur lr vout+ rtn i p i s l l d2 d1 figure 16. upper switch toggle and resonant transition
fn9182 rev 2.00 page 15 of 15 april 4, 2006 ISL6753 intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2005-2006. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. shrink small outline plastic packages (ssop) quarter size outline plastic packages (qsop) notes: 1. symbols are defined in the mo series symbol list in section 2.2 of publication number 95. 2. dimensioning and tolerancing per ansi y14.5m - 1982. 3. dimension d does not include mold flash, protrusions or gat e burrs. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension e does not include interlead flash or protrusions . interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. the chamfer on the body is optional. if it is not present, a visual index feature must be located within the crosshatched area. 6. l is the length of terminal fo r soldering to a substrate. 7. n is the number of te rminal positions. 8. terminal numbers are shown for reference only. 9. dimension b does not include dambar protrusion. allowable dambar protrusion shall be 0.10mm (0.004 inch) total in excess of b dimension at maximum material condition. 10. controlling dimension: inches. converted millimeter dimen- sions are not necessarily exact. ? index area e d n 123 -b- 0.17(0.007) c a m b s e -a- b m -c- a1 a seating plane 0.10(0.004) h x 45 c h 0.25(0.010) b m m l 0.25 0.010 gauge plane a2 m16.15a 16 lead shrink small outline plastic package (0.150 wide body) symbol inches millimeters notes min max min max a 0.061 0.068 1.55 1.73 - a1 0.004 0.0098 0.102 0.249 - a2 0.055 0.061 1.40 1.55 - b 0.008 0.012 0.20 0.31 9 c 0.0075 0.0098 0.191 0.249 - d 0.189 0.196 4.80 4.98 3 e 0.150 0.157 3.81 3.99 4 e 0.025 bsc 0.635 bsc - h 0.230 0.244 5.84 6.20 - h 0.010 0.016 0.25 0.41 5 l 0.016 0.035 0.41 0.89 6 n16 167 ? 0 8 0 8 - rev. 2 6/04

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